Ground bounce can occur with high-speed digital integrated circuits (“ICs”) when multiple outputs change states simultaneously. Ground bounce can cause several undesired effects, both on the output of the switching device and on the receiving logic device. In order to avoid problems associated with ground bounce, manufacturers of ICs publish tables of guidelines for the maximum number of simultaneous switching outputs (“SSOs”) that each power/ground pair (driver) of an IC can provide without violating a specified ground bounce limit.
Ground bounce is primarily due to current changes in the combined inductance from ground pins, bond wires, and ground metallization. The internal ground level of the IC deviates from the external system ground level for a short duration (typically a few nanoseconds) after multiple outputs change state simultaneously.
The switching output is supposed to provide a logical “1” or logical “0”. Ground bounce can affect whether the switching output is properly read by receiving logic because the logical state is typically derived by comparing an incoming signal to the internal ground of the switching device. Noise on the signal and/or ground can alter the logical state read by the receiving logic and cause erroneous operation of the system if the ground bounce amplitude exceeds the instantaneous noise margin. For example, ground bounce noise on a non-changing input that raises the internal ground level above the instantaneous noise margin might unintentionally toggle the logical state of a receiving logic input. In other words, the ground bounce can be interpreted as a switched signal on an input that isn't being switched.
The ground bounce limit is set according to the most sensitive input driven by the switching device. Given a ground bounce limit, the number of SSOs (“drivers”) allowed on a power/ground pair is set according to several assumptions. Manufacturers print tables of SSO guidelines for various types of logic, drivers, and packages. The SSO guidelines assume various values for parameters that affect ground bounce voltage.
Weighted average SSOs (“WASSOs”) are often calculated for adjacent I/O banks of a digital switching device to model device operation and account for simultaneous switching events. Ground bounce voltage performance of the adjacent I/O banks is evaluated by comparing the average WASSO for the adjacent I/O banks against the SSO allowance. If the average WASSO exceeds a selected amount, techniques are applied to reduce ground bounce in the digital system.
Time delay creep, also known as propagation delay degradation, is a time-related phenomenon associated with SSO events that can occur in a physical device and cause the physical device to operate in a fashion that is different from the expected operation based on the device simulation. Propagation delay, as measured to the input threshold level of the receiving port or device, becomes longer due to inductive ground bounce voltage on the output of the transmitting port or device (e.g., the NMOS output driver of a CMOS I/O port). The decreased current through the output driver results in more time required to charge the input capacitance of the receiving port. A conventional response to account for propagation delay degradation is to physically measure evaluation devices and compare measured performance against a specified maximum value of time delay.
Techniques for more accurately accounting for propagation delay degradation associated with ground bounce events are useful and desirable.